A typical computer system includes multiple data buses that facilitate the flow of data between various components of the system. In general, the data buses are of different types that operate according to different functional standards, such as the Industry-Standard Architecture (ISA), Extended Industry-Standard Architecture (EISA), Peripheral Component Interface (PCI), and Small Computer System Interface (SCSI) standards. Among the characteristics that distinguish the different types of data buses is operating frequency, or the rate at which a bus transfers data among components residing on the bus. In a typical computer system, data routinely is transferred between devices located on different buses operating at different frequencies. For example, a microprocessor located on a host bus operating at 50 MHz often must deliver data to a device located on a PCI bus operating at 8 MHz. To compensate for such disparities in operating frequency, the computer system must include a buffering system between the data buses.
Conventional buffering systems employ standard memory devices as first-in, first-out (FIFO) buffers. A typical FIFO buffer usually has two ports, one of which receives data from a first bus at a first data rate while the other delivers the data to a second bus at a second data rate. FIFO buffering schemes require careful synchronization of read and write controllers to prevent data from overflowing or underflowing the FIFO buffers. Some FIFO buffering schemes use multiple memory devices to create multiple FIFO buffers, such as in the well-known "double-buffering" techniques, where one of a pair of separately addressable buffers has data written to it while the other buffer is being read. The roles of the separate buffers are periodically switched.
Various techniques have been used to work around the buffer synchronism problem. One technique is to have the write side and the read side of a single buffer operate in a mutually exclusive fashion. Write control logic puts data into the buffer until the buffer is full, and then signals read control logic to start reading the content. When the reading is completed, the read control logic signals the write control logic to start filling the buffer again. This process continues until all data is transferred. This is a fool-proof method to guarantee the data integrity, but the drawback is long latency since at least one side of the buffer is idle at any given time.
Another method of determining FIFO full/empty status is by comparing the read and the write pointers of a FIFO. If the two pointers line up and the last operation is a write command, the FIFO is full. If the last operation is a read command when the two pointers lines up, the FIFO is empty. This method works well when the read and write control logic are both running at the same clock speed. When the two sides are running at two different clock speeds, there is a potential to produce an erroneous or inconclusive empty/full status, and thus there may be a danger of data corruption.
Accordingly, the inventors have concluded that a better approach is need to buffering data that flows between buses operating at different frequencies. The present invention provides a system and method for achieving this objective.